1. Field of the Invention
The present invention relates to an integrated circuit having a resistor.
2. Description of the Prior Art
Integrated circuits (ICs) often include resistors formed in doped substrate regions, which may be doped tubs, alternatively referred to as "wells" in the art. For example, a p-tub resistor or n-tub resistor may be used, which are generically referred to herein as "tub resistors". In particular, Application Specific Integrated Circuits (ASICs) typically include resistors that are located in the vicinity of the output buffers. As shown in FIG. 1, a typical output buffer comprises complementary inverter transistors 100 and 101 coupled to bondpad 103 through output resistor 102. It is usually desirable to be able to choose the resistance value (e.g., R.sub.1) of a given output resistor (e.g., 102) during the design of the IC. This allows for optimizing the output buffer drive level with respect to the anticipated load that is to be connected to the IC output terminals. For example, a relatively high impedance load is usually driven through a relatively high resistance value output resistor, in order to minimize noise due to excessive output current flow. On the other hand, a relatively low impedance load is usually driven through a relatively low value output resistor, to provide sufficient output current to drive the load at sufficiently high speed. In practice, the doping level of the substrate resistor is usually fixed by the IC process used to form the integrated circuit. Therefore, the choice of doping level is not usually available to the designer of the IC chip for determining the value of the output resistor. Rather, the size and geometry of the output resistor is usually chosen to obtain the desired resistance value.
For example, referring to FIG. 2, a prior-art output resistor is formed in a n-doped doped tub 201 located in a p-type substrate 200. A field oxide layer overlies the tub in regions 202, 203 and 204, and prevents dopants from being implanted into the tub region, except in the heavily doped (n+) contact regions 205 and 206. These contact regions are typically formed with the same dopant implant step used to form the source and drain regions of the field effect transistors (not shown). These dopants are implanted through the "thin oxide" layer that is used as the gate oxide of the transistors (not shown), and which is subsequently removed from the contact regions by etching. The substrate contact regions thereby define a substrate resistor having a length L as shown, and a width W, being the dimension perpendicular to the view shown in FIG. 2. Both the thin oxide regions and the field oxide regions are typically then overlaid by a dielectric layer, which is patterned to form regions 207, 208 and 209. The dielectric layer is typically phosphosilicate glass (PSG) or boro-phosphosilicate glass (BPSG) that is re-flowed by heating after deposition for planarization purposes, but other materials (e.g. undoped silicon dioxide) are possible, with various planarization techniques known in the art. The resistor contact regions 205 and 206 are themselves contacted by conductors that extend from an overlying conductor layer through the dielectric layer via windows 210 and 211, respectively. In this manner, connection of the resistor to other components (e.g., output buffer and bondpad) may be accomplished.
Examples of prior-art resistors are illustrated in top view in FIGS. 3 and 4. In a first example shown in FIG. 3, a relatively high resistance resistor is formed in a tub region 300 having highly doped resistor contact regions 301 and 302. The contact windows 303 and 304 extend down through the overlying dielectric (not shown for clarity) to allow the metal contact layer (not shown) to contact the respective contact regions. The resistance of this resistor is determined by the sheet resistivity of the tub region between the heavily doped contact regions, as well as the size of the tub region. Therefore, the resistance may be selected by the chip designer by the choice of the resistor length L.sub.1, which is the spacing between the contact regions, as well as the width W.sub.1 of the contact regions. In effect, the resistor width is also influence by the tub width W.sub.tub 1, so that the effective width lies between W.sub.1 and W.sub.tub 1. In a second example shown in FIG. 4, a relatively low resistance resistor is formed in a doped tub 400, with highly doped contact regions 401 and 402 being contacted through contact windows 402 and 404, respectively. The resistor in FIG. 4 is hence similar to the resistor in FIG. 3, except that the length L.sub.2 is less than L.sub.1 and the width W.sub.2 is greater than W.sub.1. Therefore, the resistor in FIG. 4 has a lower resistance value than that of FIG. 3, assuming that they are formed in otherwise identically doped tub regions.
However, it can be seen that when laying out the resistor of FIG. 4, the designer is faced with a different geometry than that of FIG. 3. Accommodating both large and small resistance values for an output buffer typically involves problems in fitting the resistors to the available free space. This is especially of concern in ASICs, where defined software library elements, the so-called "standard cells", are required. It is hence desirable to have improved techniques for forming resistors that may implement a range of resistance values in a given defined space.